In an integrated circuit, metal lines typically connect individual circuit elements together. The nature of this metal interconnect critically affects the performance and cost of the integrated circuit product. For example, most integrated circuit processes offer multiple levels of metal interconnect, in order to allow the maximum flexibility in circuit layout. This layout flexibility allows a designer to minimize the size of an integrated circuit, for example, reducing the cost of the product.
An example of a typical circuit layout with two levels of metal interconnect is shown in FIG. 1. This layout includes two metal-oxide-semiconductor field effect transistors (MOSFET) 240. Isolation edges 235 and gate fingers 240g define the transistors. One of the transistors 240 has two gate fingers 240g and one has three gate fingers. The gate shapes 240g and isolation edges 235 determine the source and drain regions of the transistors (240s and 240d, respectively). The drains 240d of both transistors 240 are electrically connected together, through contacts 245, first metal lines 250, inter-metal vias 270, and second metal line 280. The source regions 240s of the two transistors are connected individually through contacts 245 and first metal lines 250. The layout of FIG. 1 could be, for example, a complementary metal-oxide-semiconductor (CMOS) inverter, if one of the transistors 240 is an n-channel MOSFET and the other is a p-channel MOSFET.
In most multi-level metallization schemes, to connect upper-level metal lines to lower level metal lines or transistor electrodes (sources, drains, and gates), all of the intermediate metal layers and contacts or vias must be used. This can be seen in FIG. 1, where the second level metal line 280 is connected to transistor drains 240d through the first metal layer 250 and metal/diffusion contact 245. Thus, to connect source fingers 240s together, for example, a metal line 250 runs outside the transistor area to avoid shorting transistor sources 240s and drains 240d together. This increases the height, and thus the area, of the layout. Moreover, the width of this layout is determined by the minimum pitch of the contacted first metal lines, or the minimum pitch of the contacted source/drain regions—whichever is greater. If the minimum pitch of the contacted first metal lines is the greater of the two pitches, then this layout may be reduced in width by an alternative metallization scheme. Note that the minimum pitch of the contacted metal lines may be determined by lithographic or other process considerations, or it may be determined by electromigration concerns or other considerations/concerns.
The resistance (per unit length) and capacitance (per unit area) of the metal interconnect layers often has a direct impact on the performance of an integrated circuit. The interconnect structures and materials used affect, in turn, the resistance and capacitance of the interconnect lines. For example, the capacitance between a given interconnect line and the semiconductor substrate, or the capacitance between two interconnect lines, decreases as the vertical distance between them increases. If multiple interconnect layers are available, critical capacitances can be reduced by placing their nodes on metal layers that have more vertical separation between them.
To illustrate the origin of these parasitic capacitances, a cross-section of the layout of FIG. 1 is shown in FIG. 2. Parasitic capacitances, for example, between the gates 240g and the drain regions 240d (gate-drain capacitance) and the source 240s and drain 240d regions (off-state capacitance), are determined partly by the interconnect structure. For example, the overlap area between the first metal lines 250 and the source regions 240s forms a component of the off-state parasitic capacitance 290. The capacitance between the contact metal 245 and the transistor gates 240g contributes to the total gate-drain parasitic capacitance. Thus, the metallization scheme and layout has an effect on circuit parasitic capacitances, and therefore circuit performance.
These parasitic effects are important for high frequency and high-speed circuits. Such circuits are often implemented on semiconductor-on-insulator (SOI) technology, which was first commercialized in the late 1990s. The defining characteristic of SOI technology is that the semiconductor region in which circuitry is formed is isolated from bulk substrate by an electrically insulating layer. This insulating layer is typically silicon dioxide. The advantageous aspects of SOI technology stem directly from the ability of the insulator layer to electronically isolate the active layer from bulk substrate.
SOI technology represents an improvement over traditional bulk substrate technology because the introduction of the insulating layer isolates the active devices in an SOI structure, which improves their electrical characteristics. For example, parasitic capacitances within the semiconductor region—depletion and diffusion capacitances, for example—are often reduced in SOI devices, especially those with thin enough semiconductor layers such that the transistors are “fully-depleted.” Short-channel effects—the variation of the threshold voltage of a transistor with its channel length—are also reduced in SOI devices. For these reasons, among others, SOI is often the technology of choice for high-speed, low-power circuits. In addition, the SOI's insulating layer can act to shield the active devices from harmful radiation. This is particularly important for integrated circuits that are used in space given the prevalence of harmful ionizing radiation outside the earth's atmosphere.
Like bulk-substrate technologies, SOI technologies may also make use of multiple layers of metal interconnect. If these metal layers can be formed in such a way as to take advantage of the unique structure of SOI, cost and performance benefits can result. These performance benefits may be especially desirable for the types of circuits typically fabricated on SOI technologies—high-speed or high switching frequency, low-loss circuits.